Presently, various bus protocols are typically used to handle data transfer for local bus slave devices which contain cacheable or non-cacheable data that does not reside in main memory. A separate bus protocol is typically used for transferring cacheable data residing in main memory directly from one cache to another. Since each of the various bus protocols has a different set of control pins, the more protocols that are used within a system, the more control pins are required as well, thereby increasing system costs and complexity. Therefore, there is a need for a more efficient and less expensive bus protocol to support both cache-to-cache transfers and data transfers involving a local bus slave device.